• eASIC

  Participated · Equity · Sep 2013

  eASIC develops Single Mask Adaptable ASIC devices using a patented via-layer customizable routing fabric to enable low-cost, high-performance, fast-turn ASIC and System-on-Chip designs. The company’s technology targets mass customization by significantly reducing up-front costs compared with traditional ASICs. eASIC cites success and design wins in wireless infrastructure and the storage market, and recent high-volume wins in the automotive market. The company is privately held and headquartered in Santa Clara, California. eASIC plans to use new funding to expand its U.S. and European development organizations and to provide working capital to meet fast-growing demand for its devices. The press release frames the opportunity as driven by demand for mass customization, low cost, and fast time-to-market solutions. eASIC develops customizable, rapid-turnaround chips that aim to deliver the speed of FPGAs with the lower cost and power consumption of ASICs. The company customizes a nearly-finished chip by laying down a single metal layer to enable four-week factory delivery and reduce upfront design costs to roughly $20,000–$100,000. eASIC says its chips consume about 10–20% of the power of comparable FPGAs and that a chip design can be completed in a couple of months. The firm has shipped 90-nanometer parts since 2006 and counts customers among the top-20 semiconductor companies as well as consumer-systems firms across applications like portable video, cell phones, base stations, routers, and digital displays. Management, led by CEO Ronnie Vasishta, positions the company to capture share from the traditional ASIC market and to enable lower-volume chip startups. Financially, eASIC had raised $48 million in the new round and $80 million in total to date.

No current team members are available.